The present invention relates generally to semiconductor memory devices and methods for fabricating the same. More particularly, the present invention relates to a three-dimensional (3D) memory device having polysilicon diode isolation elements for chalcogenide memory cells and method for fabricating the same.
Prior art memory devices use two-dimensional (2D) memory cell arrays, which are formed on a top surface of a silicon substrate. The memory cells. are matrixed in a 2D array in the X-Y plane and thus addressed by X and Y address lines. The prior art memory devices also include isolation elements to select the memory cells. The isolation elements are generally made of metal oxide semiconductor (MOS) transistors.
A disadvantage with the prior art memory devices is that they are limited to the X-Y plane thus limiting memory density for such devices. That is, the MOS transistor isolation elements require physical use of the top surface of the silicon substrate to select a memory cell which limits memory cell arrays being formed in the X-Y plane on the silicon substrate.